Core unit |
Anlogic Technologies EG4S20 |
---|---|
Logical unit |
20K (LUT4/LUT5 hybrid architecture) |
SRAM |
About 130KB |
SDRAM |
Built-in 32bit bit width 64MBit |
Flash |
FPGA configuration Flash, 8Mbit User Flash, nor/nand optional |
Shipping Weight | 0.08 kg |
Shipping Dimensions | 8 × 5 × 3 cm |
Sipeed TANG PriMER FPGA Dev. Board
- Core unit: Analogic Technologies EG4S20
- Logical unit: 20K (LUT4/LUT5 hybrid architecture)
- SRAM: About 130KB
- SDRAM: Built-in 32bit bit width 64MBit
₨ 100.10 ₨ 90.09
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The Sipeed TANG PriMER FPGA Dev. Board is an innovative and versatile platform designed for developers and enthusiasts eager to explore the possibilities of field-programmable gate arrays (FPGAs). With its compact size and powerful capabilities, this board offers a wide range of applications, from embedded system development to digital signal processing and beyond. Equipped with an FPGA chip at its core, it provides ample resources for implementing complex logic designs and custom hardware accelerators. Additionally, the board features various peripheral interfaces, including GPIO pins, USB ports, and HDMI output, facilitating seamless integration with external devices and sensors. Whether you’re a seasoned FPGA engineer or a newcomer to the field, the Sipeed TANG PriMER FPGA Dev. Board offers an accessible yet robust platform for unleashing your creativity and pushing the boundaries of digital innovation.
Application scenario:
- High-speed communication interface interconnection
- Learning, debugging, and researching of soft cores such as RISC-V
- Machine vision processing
- Parallel computing acceleration
Features:
- FPC40P socket can be connected to RGB LCD, the VGA adapter board
- FPC24P socket can be connected to DVP camera, high-speed ADC module
- Resistive touch screen controller for I2C interface, used with RGB LCD
- The adjacent pins LVDS are drawn in the same length, leading out 8 GCLKs, and all 8 ADCs are taken out.
- Double row pin spacing 900mil, compatible with breadboard development
- The half-hole leads to an extra 40 IO, and the whole board leads to 130+ IO
- Micro USB 5V power supply; 2.54mm pin
- 3.3V~5V power supply; 1.27mm stamp hole power supply
- 3-channel DCDC power supply chip, stable and efficient power supply
- independent adjustment of Bank0 IO level
Package Includes:
1 x Sipeed TANG PriMER FPGA Dev. Board
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